Several ROM structures are well known in the art. One common ROM structure is referred to as a flat-cell ROM. The flat-cell ROM occupies a very small area per memory cell compared to other known ROM structures, which is an advantage of the flat-cell ROM structure.
FIGS. 1A and 1B are diagrams illustrating a typical flat-cell ROM array 10. FIG. 1A is a diagrammatic plan view of flat-cell ROM array 10. FIG. 1B illustrates a cross-sectional view of flat-cell ROM array 10 of FIG. 1A along a line 1B-1B. With reference to FIGS. 1A and 1B, horizontal lines 100, 102, and 104 are polysilicon word lines, and vertical lines 106, 108, and 110 are BN+ (buried N+) bit lines. Bit lines 106, 108, and 110 are deposited in a silicon substrate 112. A thin gate oxide 114 is deposited over silicon substrate 112 to form an insulation layer and word line 102 is deposited over thin gate oxide 114. Each cell of flat-cell ROM array 10 includes a field effect transistor (FET), such as transistors M0˜M5 shown in FIG. 1A, formed between two adjacent bit lines under one of the word lines, to store a bit of data. For example, with reference to FIG. 1B, word line 102 forms a gate (G) of transistors M1 and M4. BN+ bit lines 106 and 108 form respective source and drain (S/D) of transistor M1 and BN+ bit lines 108 and 110 form a source and a drain (S/D), respectively, of transistor M4. Each FET can be either N-type or P-type.
FIG. 2 is a diagram illustrating a cell 200 of flat-cell ROM array 10 and a typical accessing circuit for accessing cell 200. Cell 200 of flat-cell ROM array 10 includes a field effect transistor 201. A word line 202 forms a gate of transistor 201. A source (S) of transistor 201 corresponds to a bit line 204 and is coupled to a virtual ground voltage Vss. A drain (D) of transistor 201 corresponds to a bit line 206 and is selectively coupled to either a sense amplifier 208 or a pre-charge circuit 210 by a switch 212. Cp is a parasitic capacitance of bit line 206 and Vbit is the voltage of bit line 206.
FIGS. 3A, 3B, and 3C are diagrams illustrating an example of the operation of the typical accessing circuit shown in FIG. 2 and transistors within memory cells. Transistor 201 is processed to have either a high (e.g. 3.3V) or a low (e.g., 0.7V) threshold voltage (Vth) for representing binary data. With reference to FIG. 3A, before reading data, word line 202 does not apply a gate voltage to the gate of transistor 201 and the drain of transistor 201 is coupled to pre-charge circuit 210. In this condition, transistor 201 is OFF while the parasitic capacitance Cp is pre-charged by pre-charge circuit 210 to a fixed voltage Vpre_c. After the parasitic capacitance Cp is pre-charged to the fixed voltage Vpre_c, a reading stage is commenced in which a gate voltage, e.g., 3V, is applied to the gate of transistor 201 by word line 202 and bit line 206 is coupled to sense amplifier 208. FIG. 3B illustrates the reading stage for the case when transistor 201 is processed to have a high Vth. Since the applied gate voltage is below the high Vth, transistor 201 will remain OFF and the voltage of bit line 206 will remain at Vpre_c. In this condition, sense amplifier 208, which is coupled to bit line 206, will output a high voltage signal representing binary data “1”. FIG. 3C illustrates the reading stage for the case when transistor 201 is processed to have a low Vth. Since the applied gate voltage is above the low Vth, transistor 201 is turned ON. In this condition, the voltage of bit line 206 will be discharged to virtual ground voltage Vss as the source of transistor 201 is coupled to virtual ground voltage Vss. The sense amplifier 208, which is coupled to bit line 206, will output a low voltage signal representing binary data “0”.
FIG. 4 is a diagram illustrating typical flat-cell ROM array 10 on which a path of current flow is an accessing path and is indicated by a broken line. When data is read from a specific cell 224 during the reading stage, a current flow follows a path from sense amplifier 208 to virtual ground voltage Vss through cell 224 and the accessing circuit. For example, with reference to FIG. 4, if transistor M1 of cell 224 has a low Vth, during the reading stage, transistor M1 of cell 224 is ON. As a result, a current flows from sense amplifier 208 to virtual ground voltage Vss through a transistor 220 coupled to sense amplifier 208, transistor M1 of cell 224, and a transistor 222 coupled to virtual ground voltage Vss. If transistor M1 of cell 224 has a high Vth, during the reading stage, transistor M1 of cell 224 is OFF, the accessing path is open, and current does not flow.
The time required to access any cell of flat-cell ROM array 10 is determined by the capacitance of the parasitic capacitor Cp and the resistance of the accessing path. For a given capacitance of the parasitic capacitor Cp, the minimum access time is limited by the resistance of the access path, which depends upon a length (L) of the accessing path and the number of transistors in the accessing path. With reference to FIG. 4, since at least two transistors are needed by a flat-cell ROM array 10 to couple to sense amplifier 208 and virtual ground voltage Vss, the minimum number of transistors of the accessing circuit in the accessing path is two.
FIG. 5 is a diagram illustrating an example of a conventional flat-cell ROM structure. In order to reduce the series resistance of the accessing path and parasitic capacitance, the flat-cell ROM array is divided into several blocks. An example of such a conventional flat-cell ROM structure is shown in FIG. 3 of U.S. Pat. No. 6,084,794 entitled “HIGH SPEED FLAT-CELL MASK ROM STRUCTURE WITH SELECT LINES” of Lu et al., which is reproduced as FIG. 5 herein. With reference to FIG. 5, BLs and WLs are bit lines and word lines, respectively, and BSs, such as BSi, are block selecting lines for applying block selecting signals to control block selecting transistors, such as B0˜B3. There are two cells, which are referred to as even and odd cells, located between every two adjacent bit lines under the same word line. For example, cells C00 and C01, which are referred to as even and odd cells, respectively, are located between two adjacent bit lines BL1−1 and BLi under word line WL0. ESs and OSs are even and odd selecting lines for providing even and odd selecting signals to control even selecting transistors Ei and odd selecting transistors Oi, respectively. ESi is an even selecting line for providing even selecting signals to control even selecting transistors E1, E2, and E3, and OSi is an odd selecting line for providing odd selecting signals to control odd selecting transistors O1, O2, O3, and O4. For example, if an even cell C10 of a blocki is to be read, block selecting line BSi is pulled high to turn ON the corresponding block selecting transistors B0˜B3 of the blocki and an even selecting line ESi is also pulled high to turn ON the corresponding even selecting transistors E1˜E3 of the blocks. Meanwhile, odd selecting line OSi is pulled low so that the corresponding odd selecting transistors O1˜O4 of the blocki remain OFF. Two adjacent bit lines BLi−1 and BLi are coupled to virtual ground voltage Vss and a sense amplifier (not shown), respectively, and another bit line BLi+1 is coupled to a reference voltage VBL, which is at substantially the same voltage level as the sense amplifier. The remaining bit lines are left floating. In this manner, a current flows from the sense amplifier through the even selecting transistor E1, the even cell C10, and the block selecting transistor B0 to virtual ground voltage Vss. In this design, the number of transistors of the accessing circuit in the accessing path is two, i.e., the even selecting transistor E1 and the block selecting transistor B0. As a result, in order to implement this conventional flat-cell ROM structure, multiple control signals, i.e., the block selecting signals, the odd selecting signals, and the even selecting signals, are required to control the operation of the conventional flat-cell ROM shown in FIG. 5 during the reading stage. Also, it is necessary to provide an area within an integrated circuit for a circuit to generate and provide these control signals.
FIG. 6 is a diagram illustrating another example of a conventional flat-cell ROM structure. This example of such a conventional flat-cell ROM structure is shown in FIG. 2 of U.S. Pat. No. 6,430,079 entitled “FLAT MEMORY CELL READ ONLY MEMORY” of Shiau, which is reproduced as FIG. 6 herein. With reference to FIG. 6, four control lines BS1, BS2, BS3, and BS4 for providing four control signals are required for each block of the ROM structure. For example, if a cell C10 of block i is to be read, control lines BS1i and BS3i are pulled high, while control lines BS2i and BS4i are pulled low. Bit Lines BL0 and BL1 are coupled to virtual ground voltage Vss and a sense amplifier (not shown), respectively. A current flows from the sense amplifier through a selecting transistor D1, the transistor of cell C10, and a selecting transistor A1 to virtual ground voltage Vss. If a cell C11 of block i is to be read, control lines BS1i and BS4i are pulled low, while control lines BS2i and BS3i are pulled high. A current flows from the sense amplifier through the selecting transistor D1, the transistor of cell C11, and a selecting transistor B1 to virtual ground voltage Vss. If a cell C12 of block i is to be read, control lines BS1i and BS3i are pulled low, while control lines BS2i and BS4i are pulled high. If a cell C13 of block i is to be read, control lines BS2i and BS3i are pulled low, while control lines BS1i and BS4i are pulled high. As a result, in order to implement this conventional flat-cell ROM structure, each block of the conventional flat-cell ROM structure requires four individual control signals to cooperatively control the operation of the conventional flat-cell ROM shown in FIG. 6. Also, a circuit to generate and provide these control signals is needed.
FIG. 7 is a diagram illustrating still another example of the conventional flat-cell ROM structure. This example of such a conventional flat-cell ROM structure is shown in FIG. 4 of U.S. Pat. No. 5,117,389 entitled “FLAT-CELL READ-ONLY-MEMORY INTEGRATED CIRCUIT” of Yiu, which is reproduced as FIG. 7 herein. With reference to FIG. 7, in addition to bit lines (VGN, VGN+1, VGN+2, BLN, and BLN+1) and word lines (SWLN,1˜SWLN,M), the flat-cell ROM structure of FIG. 7 includes block selecting lines (BWL) coupled to block selecting transistors, bank left selecting lines (SBL) coupled to bank left selecting transistors L1˜L10, and bank right selecting lines (SBR) coupled to bank right selecting transistors R1˜R10. In this structure, three types of control signals, i.e., block selecting signals, bank left selecting signals, and bank right selecting signals, are required to control the operation of each block of the conventional flat-cell ROM structure of FIG. 7.
If the number of required control signals is increased, the area required by the circuit to generate and provide these control signals also increases. Therefore, it is desirable to minimize the number of the control signals to reduce the overall size of the flat-cell ROM. Besides the flat-cell ROM structures shown in FIGS. 5, 6, and 7, there are a number of other conventional flat-cell ROM structures. Some examples of them are shown in U.S. Pat. Nos. 5,621,697, 5,825,683, 6,278,649, and 6,653,692. Among these conventional flat-cell ROM structures, the minimum number of required control signals to control the operation of each block of these conventional flat-cell ROM structures is three.
Referring again to FIG. 7, the length of the accessing path in the illustrated conventional flat-cell ROM structure will be different when different cells are read. Two paths are superimposed on FIG. 7 and are the accessing paths through which current flows from a sense amplifier (not shown) to virtual ground voltage Vss when a cell 101-2 coupled to word line SWLN,1 and a cell coupled to word line SWLN,M are accessed. Since the length of the accessing path determines the resistance of the accessing path, the time required to access the cell of the flat-cell ROM array shown in FIG. 7 varies from position to position depending on the location of the cell, which is due to the variable resistance of the accessing paths.
There is thus a general need in the art for flat-cell ROM structure which employs the smallest number of required control signals to control each block of the flat-cell ROM array. Moreover, the length of the accessing path to access any cell of the flat-cell ROM array is constant.